1. Field of the Invention
The present invention generally relates to integrated circuits, and, more particularly, to semiconductor device structures with gate structures having a fluorine doping profile and methods of forming according semiconductor device structures.
2. Description of the Related Art
The majority of present-day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs) or simply MOS transistors. Typically, present-day integrated circuits are implemented by millions of MOS transistors which are formed on a semiconductor substrate with a given surface area.
Basically, MOS transistors act as electronic switching elements wherein a current through a channel region, formed between source and drain regions of a MOS transistor, is controlled by a gate electrode which is typically disposed over the channel region, independent from whether a PMOS transistor or an NMOS transistor is considered. Particularly, the conductivity state of a transistor is changed by a voltage applied to the gate electrode passing a so-called threshold voltage (Vt). In general, the threshold voltage depends nontrivially on the transistor's properties, such as size, material, etc.
In efforts to build integrated circuits with a greater number of transistors and faster semiconductor devices, developments in semiconductor technologies are directed to ultra large scale integration (ULSI), which resulted in ICs of ever-decreasing size and, therefore, of MOS transistors having reduced sizes. Herein, a critical dimension (CD) is represented by a width or length dimension of a line or space that has been identified as critical to the device under fabrication for operating properly and, furthermore, which dimension determines the device performance. In present-day semiconductor technology, the CDs of microelectronic devices have been approaching the deep sub-micron regime so as to continually meet the demand for faster and also less power-consuming semiconductor devices, so-called low power devices, which allow fabricating advanced microprocessors and digital circuits. In general, it is attempted to provide semiconductor device structures having improved high energy efficiency.
However, as semiconductor devices and device features have become smaller in order to comply with requirements set by advanced integration densities, conventional fabrication techniques have been pushed to their limits, challenging their abilities to produce finely defined features at presently required scales. Consequently, developers are faced with increasing challenges and constraints due to scaling limitations which arise as semiconductor devices continue to decrease in size.
Normally, millions of individual semiconductor devices, such as PMOS transistors or NMOS transistors, are provided on a microchip for implementing IC structures. As transistor performance depends crucially on several factors, for example, on the threshold voltage, it is easy to see that it is highly nontrivial to control a chip's performance. Therefore, controlling a chip's performance generally requires keeping many parameters of individual transistors under control, especially for strongly-scaled semiconductor devices. For example, deviations in the threshold voltage of transistor structures across a semiconductor chip strongly affect the reliability of the whole chip under fabrication. In order to ascertain a reliable controllability of transistor devices across a chip, a well-defined adjustment of the threshold voltage for each transistor has to be maintained to a high degree of accuracy. As the threshold voltage alone already depends on many factors, it is necessary to provide a carefully controlled process flow for fabricating transistor devices which reliably meets all factors.
In practice, fabricated chips are often provided to customers in so-called technology platforms with which many electrical parameters are to be specified as a function of device geometries. In this regard, the dependency of the threshold voltage variation on the device geometry, and particularly on the gate length, is an important example of the parameters to be specified.
FIG. 1 illustrates very schematically a relation between a length of a semiconductor device (L in μm) plotted against the linear threshold voltage (VtLin in V). As shown in FIG. 1, scaling down transistor devices in their length dimension induces a roll-up or roll-off of VtLin. By way of example, when starting from a length dimension of around 1 μm, a VtLin roll-up of roughly around 0.1 V may be expected when scaling down to about 72 μm.
It is generally accepted that so-called short channel effects and reverse short channel effects represent an important factor when discussing the dependency of the threshold voltage on the gate length as they become more relevant at smaller scales. Herein, the relative strength of well dosages, halo dosages and the dosages of extension regions in turn may strongly affect the reverse short channel effect. In conventional device engineering, it is attempted to carefully choose implant settings for meeting as much of the device performance criteria as possible, while showing a reasonable behavior for the dependency of the threshold voltage on the gate length. However, this does not allow actively adjusting the dependency of the threshold voltage on the gate length to a desired degree because it is rather a mere consequence of the implant settings as the performance criteria (in a broad sense, covering threshold voltage, on-current, off-current etc.) dominate over possible ranges of the implant settings.
In particular, all devices with different threshold flavors (low-threshold voltage or LVT devices, super-low threshold or SLVT devices, regular threshold voltage or RVT devices and high threshold voltage or HVT devices) in advanced high-k metal gate technologies show reverse short channel effects. In practice, no solution has been proposed for reducing the above-discussed degrading effects without deteriorating the device performance.
This may be understood by considering that although, in theory, a stable and flatter dependency of the threshold voltage on the gate length may be obtained by changing implant settings of well implantation, halo implantation and source/drain extension implantation, it is not possible to simultaneously improve all performance criteria. Therefore, in practice, such approaches only provide limited space for adjustments of the dependency of the threshold voltage on the gate length, mostly on cost of lower device performance.
US Patent Publication 2010/0148271 relates to a method for gate leakage reduction and threshold voltage shift control by implanting fluorine ions into a gate dielectric. This effect is based on the observation that the threshold voltage increases by 6.7 mV when a fluorine implant dosage is increased by 1×1015 atoms/cm2 for NMOS devices (NMOS roll-up), while the threshold voltage of PMOS devices is increased by 20 mV when an implant dosage of fluorine is increased by 1×1015 atoms/cm2 (PMOS roll-up). In the framework of US Patent Publication 2010/0148271, the threshold voltages of PMOS and NMOS devices may be matched by appropriately raising the threshold voltage of PMOS devices relative to NMOS devices.
US Patent Publication 2005/0136579 discloses a method for manufacturing a metal oxide transistor having reduced 1/f noise by implanting a fluorine dopant into a polysilicon layer and diffusing the fluorine dopants into a gate dielectric material layer formed underneath the polysilicon layer by thermal annealing and to subsequently form gate electrodes.
However, these conventional approaches basically raise the threshold voltage, while, for, advanced semiconductor devices, low performance and low power consumption is desired. Therefore, it is desirable to continue in lowering threshold voltages of semiconductor devices at advancing technology nodes.
It is desirable to provide technologies at smaller technology nodes which enable reducing variations in the threshold voltage of semiconductor devices.
It is desirable to provide a method which allows for tuning the dependency of the threshold voltage on the gate length without degrading the rest of the performance indicators. Furthermore, it is desirable to provide semiconductor device structures having a stable and flat dependency of the threshold voltage on the gate length and simultaneously meeting required advanced high device performance criteria.